Also

- SPI Ports

- UARTS

- Color-Space Converters

- Bayer-Deinterlacer

- Fifos

- Block Ram

- FFTs

- DCTs

- Filters

- I2C

- AXI Master/Slave Interface

IP Cores

- JPEG IP Cores also available for AMD(Xilinx) chips(i.e. Artix, Zynq)

- JPEGs Tested in Modelsim for hundreds of images at all known  formats.

- JPEGs Tested on Terasic De2-115 board(Cyclone IV E) with Spartan's

   image processing system. Various image sizes and formats.

   Default tables and programmed tables.

JPEG Decoder(Baseline) - Cyclone IV E.

Speed       - 200 MHz

Logic         - 5637

Memory    - 43190

Multipliers - 0

JPEG Encoder(Baseline) - Cyclone IV E

Speed        - 200 MHz

logic           - 5298

Memory     - 40524 Bits

Multipliers - 0

Prog. Tabs - Yes